The DLX processor is a based on the RISC architecture and is used primarily for educational purposes. This report describes our work on the DLX architecture for the spring 2007 semester. Included in this report are our problems that we have had throughout the semester and how we corrected these problems. Problems that have not yet been corrected are also included in this report. Our current goals are also included within this document.

The main purpose of this project was to efficiently implement a SIMD performance scheme for the DLX architecture. This goal was ultimately changed due to conflicting issues between simulation and synthesizable code. The new goal was changed to implement the DLX architecture on a Xilinx Virtex II Pro FPGA board. The specific board device we are using is the XC2VP30, FF896 Flip-Chip Fine-Pitch BGA package. Our project used the VHDL code provided by Peter J. Ashenden’s case study of the DLX computer system to run and test the DLX architecture. For more information.

The main objective of this project was to utilize simulation tools for modeling a communications system that is comprised of several subsystems.  Not long ago, it could take quite some time to prototype a single industrial product whereas today a concept can be simulated and tested thus yielding meaningful data as to whether a design is feasible for further research and/or development in hardware.  This communications system was modeled in MATLAB’s Simulink with Xilinx’s System Generator for DSP. The communications system is comprised of encoder, scrambler, shaping filter, modulation with a carrier signal, and noise exhibited in the channel. For more information.

As image processing techniques and algorithms continue to advance, there is a need for systems that run these algorithms to be reconfigurable.  This need makes the Field Programmable Gate Array (FPGA) an excellent platform for image processor system development. This project set out to implement image-processing algorithms utilizing the Xilinx Virtex-II Pro, specifically on the Xilinx University Program (XUP) Development System. Images are pre-processed using Matlab to produce a gray scale matrix represented as ASCII characters, which is then stored in a .hex file.  The file will then be sent serially using the Windows Hyperterminal to the FPGA. The FPGA stores the incoming data to on-chip memory using software that runs on the FPGA through the Microblaze soft microprocessor.  The image enters the FPGA as a bit stream through the RS-232 UART, and then is stored in a FIFO single stacked 64k BRAM block.  At this point the bytes of memory can be processed with a Sobel Edge Detector filter or a Convolution filter. The filters will be imported as peripherals through the Xilinx Platform Studio (XPS) and packaged as recognized IP-Cores so the Microblaze processor can access them. The image will then be stored back in the BRAM block, into a receive buffer, and finally captured back into the PC through the Hyperterminal and stored in a .txt file. The output files can then be post-processed in Matlab to view the results as images. For more information.