Research Topics:

• Dynamic Partial Reconfiguration
• High-performance Architectures for Signal/Image Processing
• IP cores for communication (Ethernet, USB, etc).
• Harmonic Decomposition
• Fault-tolerance circuits

Current Research:

Dynamic Partial Reconfiguration of FPGAs:

• Image processing applications, e.g.: Pixel processor, FIR Filters, filterbanks, etc. The goal is to have a set of fully reconfigurable architectures so that selected pieces of hardware can be modified while the FPGA is still in operation. This will allow us to not only share FPGA resources in time, but also to dynamically control power, precision and performance of the aforementioned systems.
• IP Cores for Partial Reconfiguration: The ICAP port (Xilinx devices) allows the FPGA to dynamically reconfigure hardware pieces of it. The goal is to develop a versatile IP core that writes to the ICAP port in response to a request of the FPGA.